1. FIELD OF THE INVENTION
This invention relates to an address buffer circuit, and more particularly to an address buffer circuit in a semiconductor memory.
2. DESCRIPTION OF THE PRIOR ART
Such address buffer circuits for use in a semiconductor memory circuit are known as one disclosed in Japanese Laid-Open Patent Application No. 96640/1974 corresponding to U.S. Pat. No. 3,795,898 which aims at rapid operation with the use of a dynamic flip-flop circuit as shown in FIG. 5. In this circuit, an insulated gate type field effect transistor (hereinbelow, referred to as metal-insulator-semiconductor field-effect-transistor or MISFET Q.sub.1 serves as a transfer gate for transferring a transistor-transistor logic (TTL) level into a MISFET logic level and transmitting an address input signal Ai to the gate of a switching MISFET Q.sub.5 of a dynamic type flip-flop and to the gate of a MISFET Q.sub.8 of the output circuit. Load MISFETs Q.sub.2 and Q.sub.3 of the flip-flop serve to supply current when both a chip enable signal CE as a control signal of the memory and the clock pulse .phi. take on a "1" level (i.e. a high level; description will be made in the case of N channel MISFETs hereinbelow). The outputs A and A of the flip-flop are determined according to the input signal Ai. The MISFETs Q.sub.6 and Q.sub.8 constituting an output circuit are turned on by the respective outputs A and A and select a predetermined decoder. Further, MISFETs Q.sub.7 and Q.sub.9 constituting the output driver circuit with the MISFETs Q.sub.6 and Q.sub.8 are turned on for the period of chip-nonselection (CE = "1") and hold both the outputs ai and ai at "0".
In the address buffer circuit of the above structure, the chip enable signal CE serves as the current source for the flip-flop circuit and supplies dc current through one inverter circuit (Q.sub.2, Q.sub.4) or (Q.sub.3, Q.sub.5) of the flip-flop circuit. Therefore, the pulse generator circuit for generating the chip enable signal CE should have a large current capacity, e.g., a driver circuit of large current capacity formed of bipolar transistors is needed. This brings about problems in the system packaging.
Further, when the chip enable signal CE is "0" (ground level), the input signal Ai is "1" (high level) and the clock pulse .phi. is "1", input current is allowed to flow through the MISFETs Q.sub.1 and Q.sub.2. In this case since the number of address buffer circuits is usually over ten in a semiconductor memory circuit, the current consumption becomes large. A total memory system comprises a plurality of such semiconductor memory circuits, and hence the total current consumption becomes even larger.
Further, when a word selection line is activated, one pair of MISFETs (Q.sub.6, Q.sub.7) or (Q.sub.8, Q.sub.9) of the output circuit are turned off. Thus, the output level of the driver formed of the turned-off MISFETs floats. Then, the decoder connected to such a driver also floats. Therefore, the level of such a decoder may be easily affected by external noises or stray capacitances in the circuit formed in a semiconductor chip to cause malfunctions.